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cm65 35 usb audi o chip page 1 / 57 www.cmedia.com.tw copyright? c - media electronics inc. block diagram description the CM6535 is a usb 2.0 audio chip builds in 8051 for flexible application s w ith tri - c olors pwm led driver, two ( 2 ) - channel adc / dac and s/pdif and i2s interface makes it suit able for h eadset, n otebook/ m obile d ocking, s peaker and m icrophone applications. the internal 8051 can also be developed to dif ferent applications, such as microsoft ? lync / skype/voip device and android phone or tablet/slate docking device . the CM6535 is compatible with usb a udio class 1.0 and usb 2.0 f ull - s peed , thus it can plug and play without additional software installation on the major operation systems. the internal dac/adc and i2s support 8~ 96 khz sampling rate and 16 /24bit s resolution . the CM6535 integrates the equalizer on both playback and recording paths to compe nsate the frequency response of m icrophon e s and headphone s . the cm653 5 also integrates 512 k byte flash (including 32kb f/w programming size) and requires few passive components to make a finish product. thus, it can save the total bom cost and pcb area can be smaller. features ? usb 2. 0 full - speed com pliant ? usb audio class 1.0 comp liant ? usb human interface device (hid) class 1.1 compliant ? two ( 2 ) - channel dac & i2s for audio output interface ? two ( 2 ) - channel adc & i2s for audio input interface ? support s digital microphone i nterface ? buil t - in s/pdif input/output transmitter ? buil t - in equalizer on both playback and recording paths ? buil t - in agc on recording path ? support s dual tone generator ? support s usb suspend/resume/reset functions ? support s control, interrupt, bulk, and isochronous data transfers ? embedded 1t 8051 with 32k b yte sram and 512 k byte flash(including 32k b yte f/w programming size) ? supports omtp and ctia auto switch on a 4 - pole jack ? integ rated tri - c olors pwm led driver ? master /slave h/w i2c /spi /uart control interface for external audio devices or flash access ? built - in 3 0mw @ 32 ohm load headphone amplifier ? on chip watchdog timer c o n t r o l b u s 3 2 k s r a m m c u w i t h 5 1 2 k f l a s h m u x a g c a d c m u x d a c 2 c h a n n e l i 2 s i n m i c r o p h o n e i n l i n e i n s p e a k e r / h e a p h o n e 2 c h a n n e l i 2 s o u t s p d i f o u t g p i o x 1 2 p w m l e d x 3 u a r t , i 2 c , s p i u s b i n t e r f a c e s p d i f i n - 1 8 ~ 4 5 d b - 3 0 ~ 3 3 d b - 3 0 ~ 3 3 d b - 3 0 ~ 1 2 d b - 1 5 ~ 3 2 d b - 4 4 ~ 0 d b - 1 6 ~ 1 2 d b - 6 2 ~ 0 d b 5 - b a n d e q 5 - b a n d e q e x t e r n a l 1 2 m c r y s t a l 4 k r o m + 1 2 d b
cm65 35 usb audi o chip page 2 / 57 www.cmedia.com.tw copyright? c - media electronics inc. release notes revision date description 1 . 0 201 5 / 6 / 22 first release 1.1 201 6 / 0 2 / 1 8 1. modify i2c using example . 2. modify spi using example . 3. u pdate test pin information. 4. modify uart tx/rx pin description
cm65 35 usb audi o chip page 3 / 57 www.cmedia.com.tw copyright? c - media electronics inc. table of contents 1 description and overview ................................ ................................ ................................ .......................... 6 2 features ................................ ................................ ................................ ................................ ...................... 6 2.1 usb compliance ................................ ................................ ................................ ........................ 6 2.2 integrated 8051 micro - processor ................................ ................................ ............................... 6 2.3 control interface ................................ ................................ ................................ ........................ 6 2.4 general ................................ ................................ ................................ ................................ ....... 7 2.5 audio i/o ................................ ................................ ................................ ................................ ... 7 2.6 general firmware volume setting value ................................ ................................ ..................... 8 3 applications ................................ ................................ ................................ ................................ ............... 8 4 pin assignment ................................ ................................ ................................ ................................ ........... 9 4.1 pin - out diag ram ................................ ................................ ................................ .......................... 9 4.2 pin description ................................ ................................ ................................ ......................... 10 4.3 pin circuit diagrams ................................ ................................ ................................ ................ 13 5 usb audio topology ................................ ................................ ................................ ................................ . 14 5.1 headset topology ................................ ................................ ................................ ..................... 14 6 function description ................................ ................................ ................................ ................................ . 16 6.1 playback equalizer ................................ ................................ ................................ ................... 16 6.1.1 five (5) - band equalizer ................................ ................................ ................................ ... 16 6. 1.2 four(4) preset eq mode ................................ ................................ ................................ ... 17 6.2 recording equalizer ................................ ................................ ................................ ................. 18 6.3 recording agc ................................ ................................ ................................ ........................ 18 6.4 hid function ................................ ................................ ................................ ............................ 21 6.4.1 hid interr upt in ................................ ................................ ................................ ................ 21 6.4.2 hid get_input_report ................................ ................................ ................................ ....... 22 6.4.3 hid set_output_report ................................ ................................ ................................ ..... 23 6.5 vendor command definition ................................ ................................ ................................ ..... 24 6.5.1 vender command read ................................ ................................ ................................ ...... 24 6.5.2 vender command write ................................ ................................ ................................ .... 24 6.5.3 usb vendor requests ................................ ................................ ................................ ........ 24 6.5.4 simple process of firmware update ................................ ................................ .................. 25 6.6 i 2 s control description ................................ ................................ ................................ ............. 26 6.6.1 i 2 s interface setting ................................ ................................ ................................ .......... 26 6.6.2 basic of i 2 s bus ................................ ................................ ................................ ................ 26 6.6.3 left justified mode ................................ ................................ ................................ ........... 27
cm65 35 usb audi o chip page 4 / 57 www.cmedia.com.tw copyright? c - media electronics inc. 6.6.4 i 2 s mode ................................ ................................ ................................ .......................... 27 6.6.5 i 2 s mclk/bclk/lrck ratio and format for CM6535 ................................ .................. 28 6.6.6 i2s output enable setting and data stream path ................................ ................................ 29 6.6.7 i 2 s dsp mode ................................ ................................ ................................ ................... 30 6.7 spdif control description ................................ ................................ ................................ ........ 31 6. 7.1 spdif frame description ................................ ................................ ................................ .. 31 6.7.2 spdif out channel status ................................ ................................ ................................ . 32 6.8 digital microphone ................................ ................................ ................................ .................. 33 6.9 i 2 c interface ................................ ................................ ................................ ............................. 34 6.9.1 i 2 c mast er mode ................................ ................................ ................................ ............... 34 6.9.2 i2c - master read with clk_sync mode ................................ ................................ .............. 35 6.9.3 i 2 c master device address and control register ................................ ................................ 35 6.9.4 i 2 c master memory address pointer (map) register ................................ ......................... 35 6.9.5 i 2 c master memory address pointer (map2) register ................................ ....................... 35 6.9.6 i 2 c master data register ................................ ................................ ................................ .... 35 6.9.7 i 2 c master control and status register 0 ................................ ................................ ........ 36 6.9.8 i 2 c master control and status register 1 ................................ ................................ ........... 36 6.9.9 i 2 c master download control and status register ................................ .............................. 36 6.9.10 i 2 c master clock period setting register ................................ ................................ ........... 37 6.9.11 i 2 c slave mode ................................ ................................ ................................ ................. 38 6.9.12 i 2 c slave data register ................................ ................................ ................................ ...... 38 6.9.13 i 2 c slave status register ................................ ................................ ................................ .... 38 6.9.14 i 2 c slave memory address pointer (map) register ................................ ............................ 39 6.9.15 i 2 c slave status register ................................ ................................ ................................ .... 39 6.10 spi interface ................................ ................................ ................................ ............................. 41 6.10.1 spi registers descriptions ................................ ................................ ............................... 41 6.10.2 spi control register 0 ................................ ................................ ................................ ..... 41 6.10.3 spi control register 1 ................................ ................................ ................................ ....... 42 6. 10.4 spi interrupt ................................ ................................ ................................ ..................... 42 6.10.5 spi control register 3 ................................ ................................ ................................ ..... 43 6.11 gpio ................................ ................................ ................................ ................................ ........ 44 6.11.1 gpo data register ................................ ................................ ................................ ............. 44 6.11.2 g pi data register ................................ ................................ ................................ .............. 44 6.11.3 gpio direction control register ................................ ................................ ........................ 44 6.11.4 gpio interrupt enable mask register ................................ ................................ ................ 44 6.11.5 gpio debouncing register ................................ ................................ ................................ 44 6.11.6 gpi remote choose ................................ ................................ ................................ ........... 44 6.11.7 gpio pull - up/down ................................ ................................ ................................ .......... 45 6.12 arbitrary sine - tone generator ................................ ................................ ................................ ... 47
cm65 35 usb audi o chip page 5 / 57 www.cmedia.com.tw copyright? c - media electronics inc. 6.13 tri - colored led control setting ................................ ................................ ................................ .. 48 6.14 reset ................................ ................................ ................................ ................................ ......... 49 6.14.1 watchdog reset timer ................................ ................................ ................................ ....... 49 7 electrical characteristics ................................ ................................ ................................ .......................... 50 7.1 absolute maximum ratings ................................ ................................ ................................ ...... 50 7.2 recommended operation conditions ................................ ................................ ........................ 50 7.3 power consumption ................................ ................................ ................................ .................. 50 7.4 dc characteristics ................................ ................................ ................................ .................... 50 7.5 analog audio ................................ ................................ ................................ ............................ 51 7.6 usb transceiver ................................ ................................ ................................ ....................... 51 7.7 micropho ne bias ................................ ................................ ................................ ....................... 52 8 audio performance ................................ ................................ ................................ ................................ .. 53 8.1 dac audio quality ................................ ................................ ................................ ................... 53 8.2 adc audio quality ................................ ................................ ................................ ................... 54 8.3 a - a path audio quality ................................ ................................ ................................ ............. 55 9 package dimension ................................ ................................ ................................ ................................ ... 56
cm65 35 usb audi o chip page 6 / 57 www.cmedia.com.tw copyright? c - media electronics inc. 1 description and overview the CM6535 is a usb 2.0 audio chip builds in 8051 for flexible application s w ith tri - c olors pwm led driver, two ( 2 ) - channel adc / dac and s/pdif and i2s interface makes it suit able for h eadset, n otebook/ m obile d ocking, s peaker and m icrophone applications. the internal 8051 can also be developed to different applications, such as microsoft ? lync / skype/voip device and android phone or tablet/slate docking device . the CM6535 is compatible with usb a udio class 1.0 and usb 2.0 f ull - s peed , thus it can plug and play without additional software installation on the major operation systems. the internal dac/adc and i2s support 8~ 96 khz sampling rate and 16 /24bit s resolution . the CM6535 integrates the equalizer on both playback and recording paths to compe nsate the frequency response of microphon e s and headphone s . the CM6535 also integrates 512k byte flash (including 32kb f/w programming size) and requires few passive components to make a finish product. thus, it can save the total bom cost and pcb area can be smaller. 2 features 2.1 usb compliance ? usb 2.0 full - speed compliant ? usb audio class 1.0 compliant ? usb human interface device (hid) class 1.1 compliant ? supports usb suspend/resume/reset functions ? supports control, interrupt, bulk, and isochronous data transfers ? support synchronous and asynchronous audio data synchronization 2.2 integrated 8051 micro - processor ? embedded 8051 micro - processor to handle the comment/protocol transactions ? embedded 512 k byte spi flash(including 32kb f/w programming size) ? 32k byte ram for firmware extension and plug - in ? hid interrupts/buttons/functions can be implemented via firmware codes ? provides maximum hardware configuration flexibility with firmware code upgrade ? vid/pid/product string can program by firmware 2.3 control interface ? master /slave i2c control interface , bus speed supports 100 and 400kbit/s ? one 4 - wire spi mater / slave interface , bus speed supports from 150k to 12mbit/s ? twelve ( 1 2 ) gpio pins and firmware program mable. ? jtag debug interface ? gpios are configured as hid key and led indicators ? tri - color pwm led driver
cm65 35 usb audi o chip page 7 / 57 www.cmedia.com.tw copyright? c - media electronics inc. 2.4 general ? s ingle 12mhz crystal input is required ? single 5 v power supply (embedded 5 v to 1.8 v regulator for digital core , 5v to 3.3v regulator for digital io, 5v to 3. 6 v regulator for analog codec ) ? 3.3v digital i/o pads with 5v tolerance ? industrial standard lqfp - 6 4 package ( 7 x 7 mm) 2.5 audio i/o ? playback stream: ? speaker/headphone ? sample rates: 8k/11.025k/16k/22. 0 5k/32k/ 44.1k/48 k /88.2k/96k hz ? support ed bit length: 16 /24 bit s ? speaker gain range(analog) is - 44 ~ 0db, 1db/step ? dac gain range ( d igital) is - 62 ~ 0db, 1db/step ? i2s interface with dsp mode ? sample rates: 8k/11.025k/16k/22.05k/32k/44.1k/48/88.2/96k ? support ed bit length: 16/24 bits ? s/pdif transmitter ? sample rates: 44.1k/48k /88.2k /96k ? support ed bit length: 16 /24 bits ? recording stream: ? microphone /line input ? sample rates: 8k/11.025k/16k/22.05k/32k/44.1k/48k/96kh ? support ed bit length: 16 /24 bits ? microphone gain range(analog) is - 18 ~ 45db, 1db/step ? line in put gain range(analog) is - 33 ~ 30db, 1db/step ? adc gain range ( d igital) is - 16 ~ 12 db, 1db/step ? i2s interface with dsp mode ? sample rates: 8k/11.025k/16k/22.05k/32k/44.1k/48k/96kh ? support ed bit length: 16/24 bits . ? s/pdif transmitter ? sample rates: 44.1k/48k /88.2k /96kh ? support ed bit length: 16/24 bits ? stereo mixer ? mix playback stream with microphone and l ine input ? g ain r ange (analog) is - 30 ~ 33db, 1db/step
cm65 35 usb audi o chip page 8 / 57 www.cmedia.com.tw copyright? c - media electronics inc. ? a - a path stream : ? microphone to playback a - a path ? mix mono microphone input to stereo playback both l/r channel . ? g ain r ange (analog) is - 15 ~ 3 2db, 1db/step . ? line in put to playback a - a path ? mix line input to stereo playback both l/r channel . ? g ain r ange (analog) is - 30 ~ 12 db, 1db/step . **note 1: a - a path means analog to analog mixer path **note 2: cm653 5 is a usb 2.0 f ull - s peed audio device. since there is a bandwidth limitation, cm653 5 cannot support 96 khz/24bits for playback and capture streams simultaneously. the possible combinations are shown below: playback capture audio format stereo, 96khz/24bits s tereo, 48k hz/24bits or below mono, 96khz/24bits or below s tereo, 48k hz/24bits or below stereo, 96khz/24bits mono, 96khz/24bits or below 2.6 general firmware volume setting value the cm653 5 is a mcu base usb audio device; the default topology is different from its h ardware capability. p lease refer to c hapter 5.1 for the CM6535 default topology while below the gain volume range. device minimum maximum default db/step speaker - 45 db (mute) 0db - 10db 1db mic rophone in put recording volume 0db +30db +20db 1db mic rophone a - a path (playback) - 15db (mute) +22db 0db 1db line in put recording volume - 26db +12db 0db 1db line in put a - a path volume - 30db +12db 0db 1db 3 applications ? usb headset ? notebook/ net book docking ? android phone/ tablet docking ? usb dac, headphone amplify ? usb mic rophone
cm65 35 usb audi o chip page 9 / 57 www.cmedia.com.tw copyright? c - media electronics inc. 4 pin assignment 4.1 pin - out diagram c m 6 5 3 5 l q f p - 6 4 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 3 2 3 1 3 0 2 9 a v 4 2 _ d a a v d d 5 0 a v d d 4 2 a v d d 3 6 a g n d m b i a s r _ s l e e v e m i c r _ r i n g 2 m i c _ s w o u t v a g m b i a s l m i c l a v 3 6 _ d a l l o u t l g p i o _ 0 p d s w t e s t i 2 c _ s c l k v s s u s b _ d p d v d d 1 8 d v d d 5 0 v s s a g n d d n _ i p o d d p _ p c 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 4 8 4 7 4 6 4 5 g p i o _ 9 g p i o _ 1 0 g p i o _ 1 1 d a c _ d i n d a c _ l r c k d a c _ d o u t d a c _ b c l k d a c _ m c l k a v 3 6 _ d a r l o u t r a d c _ d o u t s p d i f _ i s p d i f _ o g p i o _ 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 g p i o _ 4 g p i o _ 3 a d c _ d o u t a d c _ l r c k a d c _ d i n a d c _ b c l k a d c _ m c l k g p i o _ 7 g p i o _ 6 v s s s p i _ m i s o s p i _ m o s i s p i _ c s 0 s p i _ s c k g p i o _ 2 g p i o _ 1 i 2 c _ s d a t x t a l _ i x t a l _ o d n _ p c u s b _ d m d v d d 3 3 l i n e i n r l i n e i n l v o l a d j a g n d _ d a r l o c o m a g n d _ d a l g p i o _ 5 g p i o _ 1
cm65 35 usb audi o chip page 10 / 57 www.cmedia.com.tw copyright? c - media electronics inc. 4.2 pin description pin # symbol i/o description clock 8 xtal_o ao 12mhz crystal oscillator output 7 xtal_i ai 12mhz crystal oscillator input usb2.0 bus interface 10 usb_dp aio usb 2.0 data plus (usb d+ signal) 11 usb_d m aio usb 2.0 data minus (usb d - signal) power/ground 12 dvdd33 ao regulator 3.3v output, drive capacity 10ma 13 dvdd18 ao regulator 1.8v output, no current drive capacity 14 dvdd50 pwr 5v digital power for 5/3.3/1.8v regulator 27 avdd36 ao analog 3.6v regulator for adc, no current drive capacity 28 avdd42 ao 4.2v power for analog and voltage and current reference 29 avdd50 pwr 5v analog power for 4.2/3.6v regulator 30 av42_da ao analog 4.2v regulator for analog 3.6v regulator, no current drive capacity 31 av36_dal ao analog 3.6v regulator for dac left channel, no current drive capacity 37 av36_dar ao analog 3.6v regulator for dac right channel, no current drive capacity 9 vss gnd digital ground 59 vss gnd digital ground 15 vss gnd digital ground 16 agnd gnd analog ground 26 agnd gnd analog ground 33 agnd_dal gnd analog ground 35 agnd_dar gnd analog ground audio interface 23 mic_swout ai combo jack detect and auto switch, detect combo jack type and switch to micr_ring2 or mbiasr_sleeve. 20 micl ai mic rophone in left channel 24 micr_ring2 ai mic rophone in right channel or combo jack r ing2 pin input 21 mbiasl ao microphone bias (2.75v) for l eft channel 25 mbiasr_sleeve ao microphone bias (2.75v) for r ight channel or combo jack sleeve pin input 22 vag ao voltage reference cap filter 32 loutl ao line out left channel 34 locom ao line out common reference for cap - less connection suggest ed connections: cap - less: 10uf none use: floating 36 loutr ao line out right channel 18 lineinl ai line in put left channel 19 lineinr ai line in put right channel 17 voladj ai analog control voltage input for playback volume control sar adc digital input range: sarad<5:0> 000000:maxium ------ 27.3mv 111111:minium ------- 1.75v (27.3mv/1step) two ( 2 ) - channel i2s dac o utput i nterface 38 dac_mclk d i o i2s out master clock programmable 3.3v output buffer
cm65 35 usb audi o chip page 11 / 57 www.cmedia.com.tw copyright? c - media electronics inc. 39 dac_bclk dio i2s out bit clock programm able 3.3v bidirectional buffer internal default pull - down 40 dac_dout do i2s out serial data output programmable 3.3v output buffer 41 dac_lrck dio i2s out left/right clock programm able 3.3v bidirectional buffer internal default pull - down 42 dac_din di i2s out serial data input , for dsp mode only programmable 3.3v output buffer two ( 2 ) - channel i2s adc i nput i nterface 52 adc_ dout do i2s in serial data output ; f or dsp mode only 53 adc_ lrck dio i2s in left/right clock programm able 3.3v bidirectional buffer internal default pull - down 54 adc_ din di i2s in serial data input programmable 3.3v input buffer, schmitt trigger internal default pull - down 55 adc_ bclk dio i2s in bit clock programmable 3.3v bidirectional buffer internal default pull - down 56 adc_ mclk d i o i2s in master clock programmable 3.3v output buffer s/pdif i/o 47 spdif_o do s/pdif transmitter spdif_o is an output buffer with 8ma tri - state 48 spdif_i di s/pdif receiver spdif_o is an input buffer with 8ma tri - state gpio 2 gpio_0 dio general purpose input/output (default volume up button). 3.3v i/o, 5v tolerance, bidirectional buffer with 8ma driving current, default weak pull - up for input (jtag - tck) 1 gpio_1 dio general purpose input/output (default volume down button). 3.3v i/o, 5v tolerance, bidirectional buffer with 8ma driving current, default weak pull - up for input (jtag - tms) 64 gpio_2 dio general purpose input/output (default play mute button). 3.3v i/o, 5v tolerance, bidirectional buffer with 8ma driving current, default weak pull - up for input (jtag - tdi) 51 gpio_3 dio general purpose input/output (default rec mute button). 3.3v i/o, 5v tolerance, bidirectional buffer with 8ma driving current, default weak pull - up for input. 50 gpio_4 dio programmable 2 in 1 i/o interface. gpio/pwm select by firmware. general purpose input/output (default pwm led blue). 3.3v i/o, 5v tolerance, bidirectional buffer with 8ma driving current, default weak pull - up for input. 49 gpio_5 dio programmable 2 in 1 i/o interface. gpio/pwm select by firmware. general purpose input/output (default pwm led green). 3.3v i/o, 5v tolerance, bidirectional buffer with 8ma driving current, default weak pull - up for input. 58 gpio_6 dio programmable 2 in 1 i/o interface. gpio/pwm select by firmware. general purpose input/output (default pwm led red). 3.3v i/o, 5v tolerance, bidirectional buffer with 8ma driving current, default weak pull - up for input (jtag - trst)
cm65 35 usb audi o chip page 12 / 57 www.cmedia.com.tw copyright? c - media electronics inc. 57 gpio_7 dio general purpose input/output (jtag - tdo). 3.3v i/o, 5v tolerance, bidirectional buffer with 8ma driving current, d efault eq disable weak pull - up for input. there are 4 kinds of preset eq, gpio7 and 8 are used to determine in which mode. the combinations are shown below. gpio[8:7]=0,0: normal mode gpio[8:7]=0,1: gaming mode gpio[8:7]=1,0: communication mode gpio[8:7]=1,1: movie mode eq function can enable via configuration tool or firmware. 46 gpio_8 dio general purpose input/output 3.3v i/o, 5v tolerance, bidirectional buffer with 8ma driving current, default eq disable weak pull - up for input. 45 gpio_9 dio general purpose input/output (default rec clip indicator). 3.3v i/o, 5v tolerance, bidirectional buffer with 8ma driving current, default weak pull - up for input. 44 gpio_10 dio programmable 3 in 1 i/o interface. gpio/digital mic clock (dmic_clk)/ uart _ rx select by firmware . gpio (default mic jack detect): 3.3v i/o, 5v tolerance, bidirectional buffer with 8ma driving current, default weak pull - up for input. 43 gpio_11 dio programm able 3 in 1 i/o interface. gpio/digital mic data (dmic_dat)/ uart _ tx select by firmware . gpio (default headphone jack detect): 3.3v i/o, 5v tolerance, bidirectional buffer with 8ma driving current, default weak pull - up for input. 4 - wire spi serial bus 60 spi_miso dio spi data master in/slave out, 3.3v i/o, 5v tolerance, bidirectional buffer with 8ma driving current, default weak pull - down for input. 61 spi_mosi dio spi data master out/slave in, 3.3v i/o, 5v tolerance, bidirectional buffer with 8ma driving current, default weak pull - down for input. 62 spi_cs0 dio spi chip select, 3.3v i/o, 5v tolerance, bidirectional buffer with 8ma driving current, default weak pull - up for input. 63 spi_sck dio spi clock, 3.3v i/o, 5v tolerance, bidirectional buffer with 8ma driving current, default weak pull - down for input. 2 - wire serial bus (i2c) 6 i2c_sdat dio 2 - wire serial data, 3.3v i/o, 5v tolerance , bidirectional b uffer with 8ma driving current default weak pull - up for input. 5 i2c_sclk dio 2 - wire serial clock, 3.3v i/o, 5v tolerance , bidirectional b uffer with 8ma driving current default weak pull - up for input. miscellaneous 3 pdsw do power down switch is an output buffer with 8ma tri - state output. normal mode: 0 suspend mode: 1 4 test di the test pin is used for ic test, another one is in the in s tance when f/w crash es or usb was not recognized, s et test pin to 3.3v before usb connect can force mcu into boot loader mode and be able to update f/w via configuration tool, d efault weak pull - down for input. 1: boot loader mode 0 : normal operation **note 1 : gpios, i2c, spi, spdif , mic_swout, micl , micr_ring2, mbiasl, mbiasr_sleeve, vag, lou tl, locom, loutr, voladj, pdsw pins can be left floating if not in use. **note2: suggest connect test pin to gnd by default setting.
cm65 35 usb audi o chip page 13 / 57 www.cmedia.com.tw copyright? c - media electronics inc. 4.3 pin c ircuit d iagrams vag, mic_bais analog input pins line, mic output pins loutl, loutr output pins loutl, loutr a g n d v a g v s s a d c a g n d a g n d l o u t _ n v r e g v d d v s s
cm65 35 usb audi o chip page 14 / 57 www.cmedia.com.tw copyright? c - media electronics inc. 5 usb audio topology 5.1 headset topology usb interfaces list interface description endpoint interface 0 audio control interface interface 1 audio stream interface for playback 0x01 interface 2 audio stream interface for record 0x82 interface 3 hid interface 0x87(interrupt in 16 bytes) s p e a k e r 2 c h o u t u s b s t r e a m i n g i n t e r f a c e # 1 0 1 0 7 0 5 o t i t m u t e c o n t r o l v o l u m e c o n t r o l - 4 5 d b ( m u t e ) ~ 0 d b m i c r o p h o n e 2 c h i n 0 2 0 6 o t i t u s b s t r e a m i n g i n t e r f a c e # 2 0 8 0 e m i x e r 0 b m u t e c o n t r o l v o l u m e c o n t r o l 0 d b ~ 3 0 d b m u t e c o n t r o l v o l u m e c o n t r o l - 1 5 d b ( m u t e ) ~ 2 2 d b l i n e i n p u t 2 c h i n i t s p d i f 2 c h i n i t 0 3 0 4 0 9 0 a 0 c ? m u t e c o n t r o l v o l u m e c o n t r o l - 3 0 d b ~ 1 2 d b 0 d m u t e c o n t r o l v o l u m e c o n t r o l - 3 0 d b ~ 1 2 d b m u t e c o n t r o l s e l e c t o r
cm65 35 usb audi o chip page 15 / 57 www.cmedia.com.tw copyright? c - media electronics inc. audio stream interfaces alternate setting list interface 1 (speaker) alt 1 2 ch, 16 b its pcm 8k,11.025k,16k,22.05k,32k ,44.1k,48k alt 2 2 ch, 24 b its pcm 8k,11.025k,16k,22.05k,32k ,44.1k,48k alt 3 2ch, 16 b its pcm 88.2k,96k alt 4 2ch, 24 b its pcm 88.2k,96k interface 2 (mic in, line - in, spdif - in) alt 1 2ch, 16 b its pcm 44.1k,48k alt 2 2ch, 24 b its pcm 44.1k,48k alt 3 2ch, 16 b its pcm 88.2k,96k alt 4 2ch, 24 b its pcm 88.2k,96k
cm65 35 usb audi o chip page 16 / 57 www.cmedia.com.tw copyright? c - media electronics inc. 6 function description 6.1 playback equalizer 6.1.1 five ( 5 ) - band equalizer cm65 3 5 has integrated five ( 5 ) - band hardware digital equalizer (eq) engine inside the chips to prov i de various application usages. it provides up to four ( 4 ) - preset modes on c lient s product design for different user scenarios including default/music, movies , g am ing and communication modes. c lient s could also change the gain parameters for each of the preset application eq mode via embedded flash coding. also , the eq engine could also be utilized for compensating and fine - tuning the headphone driver for sound pressure level ( spl ) performance to a s pecific preference . in this case, c lient s could fully customize all eq coefficients such as center frequenc y , gain values, and bandwidth to one optimized frequency response curve and setting in terms of the headphone driver and housings acoustics characte ristics , also via embedded flash programming . the eq engine contains five ( 5 ) frequency bands (fc) of digital filters to conduct transfer functions of the frequency response over the audio band. it allows maximum of + - 12db digital gain (gain) for each band with 0.5db adjustment per step. each filter will have its bandwidth (bw) fac tor between 0 and 1.0. fc: center frequency, f1~f5, 20 cm65 35 usb audi o chip page 17 / 57 www.cmedia.com.tw copyright? c - media electronics inc. three ( 3 ) eq usage/application scenarios no scenario gain value center frequency / bandwidth factor number of modes user control type 1 4 switchable presets configurable fixed 4 hardware 2 full - customized eq configurable configurable 1 n.a. 3 treble/bass feature unit configurable configurable 1 software ** note: in the user control type, h ardware means end - users could select which eq mode will be use d by a hardware switch/button on the product while s oftware control means they could control the treble/bass gain values by gui in windows os sound device advanced settings. 6.1.2 four( 4 ) p reset eq m ode as mentioned above, eq engine already provides four (4) - preset eq modes for different user scenarios/applications. the eq function default was disable d but it can be enable d via configuration tool or firmware, e nd users could use the hardware switch on the product (determined by 2 eq configuration input pins) to dynamically change to different eq modes. the following shows the frequency response of each mode : mode gpio8 gpio7 color default 0 0 ---------------- gaming 0 1 ---------------- communication 1 0 ---------------- movie 1 1 ----------------
cm65 35 usb audi o chip page 18 / 57 www.cmedia.com.tw copyright? c - media electronics inc. 6.2 recording equalizer cm653 5 also provide five ( 5 ) - band e qualizer for the input. it can be used to compensate the frequency response of m icrophone unit. c lient s could fully customize all eq coefficients (center frequency, gain values, and bandwidth) through embedded flash coding . 6.3 recording agc automatic gain con trol (agc) is an automatically controlled method to adjust with intensity of signal . agc closes the return circuit and that is by the negative response system too. agc is also for compressing volume, first it w ill increase gain when it is started, then it will s et up the upper and lower limits of the signal and lastly, it will compress the dynamic range of sound. agc is used usually for recording and producing sound, or when volume is being changed in a small environment. if the volume is low , agc will increase the volume hence if volume is sustained loudly, agc will decrease volume. features programmable agc parameters selectable gain from C 12 db to 45 db in 1 - db steps selectable attack, release and hold times agc enable/disable function limiter enable/disable function pre - detect limiter level function two (2) - channel agc independent d efault c ommunication m ovie gaming audio precision 04/20/11 15:35:35 da-eq-spdif_in_da_out.at27 color sweep trace line style thick data axis comment 1 1 red solid 2 anlr.ampl left 00 2 1 magenta solid 2 anlr.ampl left 11 3 1 cyan solid 2 anlr.ampl left 10 4 1 blue solid 2 anlr.ampl left -10 +1 -9 -8 -7 -6 -5 -4 -3 -2 -1 -0 d b r a 20 20k 50 100 200 500 1k 2k 5k 10k hz
cm65 35 usb audi o chip page 19 / 57 www.cmedia.com.tw copyright? c - media electronics inc. shown b elow are input source types to set agc gain max/min limit i2s rec +12~ - 16db 0xf9= 0x1c (max)+fix gain(9db) = 0x25 0cfa= 0x00(min) dig ital mic rophone +20 ~ - 16db 0xf9= 0x24 (max)+fix gain(9db) =0x2d 0xfa= 0x00(min) analog mic rophone +30 ~ 0db 0xf9=0x0f+fix gain(9db) inv - > 0x39(max) 0xfa=0x2d inv - > 0x12(min)
cm65 35 usb audi o chip page 20 / 57 www.cmedia.com.tw copyright? c - media electronics inc. agc variable description fixed gain: the normal gain of the device when the agc is inactive limiter level: the value that sets the maximum allowed output amplitude attack time: the minimum time between two gain decrements release time: the minimum time between two gain increments hold time: the time it takes fo r the very first gain increment after the input signal amplitude decreases i n p u t s i g n a l o u t p u t s i g n a l m a x t h r e s h o l d m a x t h r e s h o l d a t t a c k t i m e h o l d t i m e r e l e a s e t i m e d e c r e a s e g a i n h o l d g a i n i n c r e a s e g a i n
cm65 35 usb audi o chip page 21 / 57 www.cmedia.com.tw copyright? c - media electronics inc. 6.4 hid function 6.4.1 hid i nterrupt i n input data format: byte0 always 1 for org hid event report id byte1 for defined hid event, each event occupies one bit byte2 byte3 start address of returned data (h - start_addr) byte4 start address of returned data (l - start_addr) byte5 bit7 bit6:uart_int bit5:gpi_int bit4:spis_int (slave mode int) bit3: spim_int (master mode int) bit2:i2cs_int (slave mode int) bit1:i2cm_int (master mode int) bit0: ir_int byte6 read data of [start_addr] byte7 read data of [start_addr+1] byte8 read data of [start_addr+2] byte9 read data of [start_addr+3] byte10 read data of [start_addr+4] byte11 read data of [start_addr+5] byte12 read data of [start_addr+6] byte13 read data of [start_addr+7] byte14 read data of [start_addr+8] byte15 read data of [start_addr+9]
cm65 35 usb audi o chip page 22 / 57 www.cmedia.com.tw copyright? c - media electronics inc. 6.4.2 hid get_input_report command format: bmrequesttype brequest wvalue windex wlength data 8h a1 8h 01 16h 01 01 16h 00 03 16h 00 10
cm65 35 usb audi o chip page 23 / 57 www.cmedia.com.tw copyright? c - media electronics inc. 6.4.3 hid set_output_report comman d format: bmrequesttype brequest wvalue windex wlength data 8h 21 8h 09 16h 02 01 16h 00 03 16h 00 10 output data format: byte0 always 1 for org hid event report id byte1 start address of write reg (h - start_addr) byte2 start address of write reg (l - start_addr) byte3 effective write/read data length (<=12) byte4 write data to [start_addr] byte5 write data to [start_addr+1] byte6 write data to [start_addr+2] byte7 write data to [start_addr+3] byte8 write data to [start_addr+4] byte9 write data to [start_addr+5] byte10 write data to [start_addr+6] byte11 write data to [start_addr+7] byte12 write data to [start_addr+8] byte13 write data to [start_addr+9] byte14 write data to [start_addr+10] byte15 write data to [start_addr+11]
cm65 35 usb audi o chip page 24 / 57 www.cmedia.com.tw copyright? c - media electronics inc. 6.5 vendo r command definition 6.5.1 vender command read command format: bmrequesttype brequest wvalue windex wlength data 8h c3 8h 02 16h 16h 00 00 16h 00 C byte 0 data of reg[wvalue] byte 1 data of reg[wvalue + 1] byte 2 data of reg[wvalue + 2] byte 63 data of reg[wvalue + 63] 6.5.2 vender command write command format: bmrequesttype brequest wvalue windex wlength data 8h 43 8h 01 16h 16h 00 00 16h 00 C byte 0 data of reg[wvalue] byte 1 data of reg[wvalue + 1] byte 2 data of reg[wvalue + 2] byte 63 data of reg[wvalue + 63] 6.5.3 usb v endor r equests bmrequesttype brequest wvalue windex wlength data 0x43 (vendor other) 0x01 register write address 0x0000 data length (<=64 bytes) data 0xc3 (vendor other) 0x02 register read address 0x0000 data length (<=64 bytes) data 0x43 (vendor other) 0x03 flash write address 0x0000: write only 0x0001: auto verify data length (<=64 bytes) data 0xc3 (vendor other) 0x04 flash read address 0x0000 data length (<=64 bytes) data 0x43 (vendor other) 0x05 flash control 0x0000 0x0001: chip erase 0x0000 none address 0x0002: sector erase 0xc3 (vendor other) 0x06 flash control - get status 0x0000 0x0000 0x0001 1 - byte data 0x01: erasing 0x00: ready
cm65 35 usb audi o chip page 25 / 57 www.cmedia.com.tw copyright? c - media electronics inc. 6.5.4 simple p rocess of f irmware u pdate 1 . g e t r e g i s t e r 0 x 3 e h o s t d e v i c e 4 . s e n d v e n d o r c o m m a n d 0 x 0 6 t o c h e c k i f t h e e r a s e p r o c e s s f i n i s h e d 5 . u s e v e n d o r c o m m a n d 0 x 0 3 w i t h a u t o - v e r i f y o p t i o n t o w r i t e f l a s h i f t h e d a t a v e r i f i c a t i o n f a i l s , t h e d e v i c e w i l l s t a l l t h e v e n d o r c o m m a n d 6 . f i r m w a r e u p d a t e c o m p l e t e 2 . m o d i f y c s _ s e l t o c s 2 , t h e n w r i t e b a c k t o r e g i s t e r 0 x 3 e 3 . w h e n c s _ s e l i s c h a n g e d t o c s 2 , f i r m w a r e w i l l e r a s e t h e w h o l e f l a s h a u t o m a t i c a l l y r e p e a t w r i t i n g f l a s h
cm65 35 usb audi o chip page 26 / 57 www.cmedia.com.tw copyright? c - media electronics inc. 6.6 i 2 s control d escription 6.6.1 i 2 s interface setting i 2 s has three clock signals ( mclk, bclk and lrck ) and at least one data line depending on the channels supported. one data line contains two chan nels. therefore, there is one data line for a 2 - channel i 2 s dac controller. the three i 2 s c lock symbols are explained below : mclk = main clock. bclk = bit clock. lrck = left and right clock. 6.6.2 basic of i 2 s bus both master and slave modes of i 2 s are supported, namely i 2 s dac, i 2 s adc. master mode means bclk and lrck are provided as shown in the left diagram below . on the contrary, slave mode means bclk and lrck are provided by the i 2 s codecs as shown in the right diagram below . master mode slave mode figure - 1 i2s master/slave block diagram below figure illustrates the basic waveform of i 2 s. note that bclk is generated at the positive edges of mclk with the ratios 1, 1/2, 1/4, or 1/8, and lrck is generated at the negative edges of bclk with the ratios 1/64, 1/128, 1/256. data lines are trans m it t ed at the negative edges of bclk, and are sampled at the positive edges of bclk by codecs in case of playback or recording. figure - 2 i 2 s t iming d iagram i2s interface codec mclk bclk lrck i2s interface codec mclk bclk lrck msb msb 1 2 3 n - 1 n 4 lsb lsb 1 2 3 n - 1 n 4 lrck bclk din/ dout left channel right channel
cm65 35 usb audi o chip page 27 / 57 www.cmedia.com.tw copyright? c - media electronics inc. for the i 2 s dac controller, the audio data is transformed from the parallel format to the serial format before being transmitted. then, the bit data is shifted out one by one with the msb first via dout signal. if the i 2 s dac controller is set to 32 bits, at least 32 bclk clocks must exist in both lrck left and right channels. in the same manner, the audio data is transformed from serial format to the parallel format fo r the i 2 s adc controller. 6.6.3 left justified mode in the left justified mode of the i 2 s dac controller, the msb data bit is clocked out at the negative edge of bclk which is aligned to the transition of lrck. in the left justified mode of i 2 s adc controllers, the msb data bit is clocked out by codecs and sampled at the first positive edge of bclk which follows a lrck transition. lrck is high during left channel transmission and low during right channel transmission in the left justified mode. figure - 3 left justified m ode t iming d iagram of i 2 s 6.6.4 i 2 s mode in the i 2 s mode of the i 2 s dac controller, the msb data bit is clocked out by CM6535 at the first negative edge of bclk which follows a lrck transition. in the same manner , the msb data bit is clocked out by code c s and sampled at the second positive edge of bclk which follows a lrck transition. lrck is low during left channel transmission and high during right channel transmission in the i 2 s mode. figure - 4 i 2 s m ode t iming d iagram of i 2 s msb msb 1 2 3 n - 1 n 4 lsb lsb 1 2 3 n - 1 n 4 lrck bclk din/ dout left channel right chan nel where the msb is clocked out the msb is sampled here msb msb 1 2 3 n - 1 n lsb lsb 1 2 3 n - 1 n lrck bclk din/ dout left cha nnel right channel where the msb is clocked out the msb is sampled here 1 bclk 1 bclk
cm65 35 usb audi o chip page 28 / 57 www.cmedia.com.tw copyright? c - media electronics inc. 6.6.5 i 2 s mclk/bclk/lrck ratio and format for CM6535 i2s clock format sampling freq. resolution format bclk/lrck mclk/lrck master mode 8/11.025/16/ 22.5/32/44.1/48 16/24 bits left justified / i2s - mode 64 256/512 88.2/96 16/24 bits left justified / i2s - mode 64 256 slave mode mclk from CM6535 8/11.025/16/ 22.5/32/44.1/48 16/24 bits left justified / i2s - mode 64 256/512 88.2/96 16/24 bits left justified / i2s - mode 64 256 slave mode mclk from external 8/11.025/16/ 22.5/32/44.1/48 /88.2/96 16/24 bits left justified / i2s - mode 64 128/256/512
cm65 35 usb audi o chip page 29 / 57 www.cmedia.com.tw copyright? c - media electronics inc. 6.6.6 i2s output enable setting and d ata s tream p ath pin - out - en ext - i2s - master ext - i2s - slave with mclk - out ext - i2s - slave with mclk - in int - i2s - master int - i2s - master with dsp codec_sel=1 codec_sel=1 codec_sel=1 codec_sel=2 codec_sel=3 adcmk_ext 0 0 1 0 0 adc_mken 1 1 0 0 1 adc_blken 1 0 0 0 1 adc_dspen 0 0 0 0 1 dacmk_ext 0 0 1 0 0 dac_mken 1 1 0 0 1 dac_blken 1 0 0 0 1 dac_doen 1 1 1 0 1
cm65 35 usb audi o chip page 30 / 57 www.cmedia.com.tw copyright? c - media electronics inc. 6.6.7 i 2 s dsp mode the CM6535 i 2 s interface supports dsp mode. the audio signal can be passed through external dsp processing and returned back to internal dac/adc for audio data convert. usb playback stream dsp m ode a udio d ata f low usb capture stream dsp m ode a udio d ata f low c m 6 5 3 5 u s b p l a y b a c k s t r e a m d s p d a c _ d o u t d a c _ d i n d a c a n a l o g o u t c m 6 5 3 5 u s b c a p t u r e s t r e a m d s p a d c _ d i n a d c _ d o u t a d c a n a l o g i n p u t
cm65 35 usb audi o chip page 31 / 57 www.cmedia.com.tw copyright? c - media electronics inc. 6.7 spdif control description 6.7.1 spdif frame description ? audio format: linear 16 bit default. ? allowed sampling frequencies (fs) of the audio: ? 44.1 khz from cd ? 48 khz from dat ? 32 khz from dsr ? one way communication: from transmitter to receiver. ? control information: ? v (validity) bit: indicates if audio sample is valid. ? u (user) bit: user free coding i.e. running time song, track number. ? c (channel status) bit: emphasis, sampling rate and copy permit. ? p (parity) bit: error detection bit to check for good reception. ? coding format: bi - phase mark except the headers (preambles), for sync purposes. ? bandwidth occupation: 100 khz up to 6 mhz (no dc!) ? signal bitrate is 2.8 mhz (fs=44.1 khz), 2mhz (fs=32 khz) and 3.1 mhz (fs=48 khz). ? figure - 17 bi - phase mark s ignal of spdif preamble cell - order cell - order (last cell "0") (last cell "1") ------------------------------------------------------ "b" 11101000 00010111 "m" 11100010 00011101 "w" 11100100 00011011 preamble b: marks a word containing data for channel a (left) at the start of the data - block. preamble m: marks a word with data for channel a that isn't at the start of the data - block. 1 0 1 1 0 0 1 0 1 0 1 1 0 1 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 0 1 0 0 c l o c k d a t a s i g n a l b i p h a s e m a r k s i g n a l
cm65 35 usb audi o chip page 32 / 57 www.cmedia.com.tw copyright? c - media electronics inc. preamble w: marks a word containing data for channel b (right, for stereo). w hen using more than 2 channels, this could also be any other channel (except for a). the number of sub - frames that will be used will depend on the number of channels that is being transmitted. a cd - player uses channels a and b (left/right) and so each frame contains two sub - frames. a block contains 192 frames and starts with a preamble "b": v: valid, u: user - data, c:channel - status - data, p:parity - bit figure - 5 spdif s ubframe d escription in each block, 384 bits of channel status and subcode info are transmitted. the channel - status bits are equal for both sub - frames, so actually only 192 useful bits are transmitted: figure - 6 preamble description of 192 spdif frame 6.7.2 spdif out channel status bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 byte0 consumer /professional audio/ non - audio copyright pre - emphasis mode default 0(p) 0(p) 1(p) 0(p) 0(fixed) 0(fixed) 0(fixed) 0(fixed) byte1 category code l default 0(p) 0(p) 0(p) 0(p) 0(p) 0(p) 0(p) 0(p) byte2 source number channel number default 0(fixed) 0(fixed) 0(fixed) 0(fixed) 0(fixed) 0(fixed) 0(fixed) 0(fixed) byte3 sampling frequency clock accuracy reserved default 0(p) 0(p) 0(p) 0(p) 0(fixed) 0(fixed) 0(fixed) 0(fixed) note p: these bit s can be programmed by usb hid or usb vendor command p r e a m b l e a u x d a t a l s b a u d i o d a t a m s b v u c p 0 3 4 7 8 2 7 2 8 2 9 3 0 3 1 s u b - f r a m e c h a n n e l a m c h a n n e l a w c h a n n e l a b c h a n n e l a w c h a n n e l a m c h a n n e l a w f r a m e 1 9 1 f r a m e 0 f r a m e 1 s u b f r a m e s u b f r a m e
cm65 35 usb audi o chip page 33 / 57 www.cmedia.com.tw copyright? c - media electronics inc. 6.8 digital mic rophone cm653 5 provide digital microphone interface for recording. there are two microphone signals transmitted on a single data line from dmic module. the oversampling bit stream output from dmic module connects to internal decimation filter to generate pcm output. clock data1 data2 dat a clock l/r gnd in vdd dat a clock dmic module mic vdd cm653 5
cm65 35 usb audi o chip page 34 / 57 www.cmedia.com.tw copyright? c - media electronics inc. 6.9 i 2 c interface 6.9.1 i 2 c master mode i 2 c protocol timing a a a a s l a v e a d d r e s s 0 m a p a d d r e s s d a t a 0 d a t a 1 a a s l a v e a d d r e s s 0 m a p a d d r e s s a s l a v e a d d r e s s 1 a d a t a 0 w r i t e t r a n s a c t i o n r e a d t r a n s a c t i o n f r o m m a s t e r t o s l a v e f r o m s l a v e t o m a s t e r s c l 0 a a a a m a p d a t a 1 s d a 1 . n b y t e w r i t e t r a n s a c t i o n s l a v e a d d r e s s 1 a d a t a 1 s d a 2 . n b y t e r e a d t r a n s a c t i o n s l a v e a d d r e s s a a f r o m m a s t e r t o s l a v e f r o m s l a v e t o m a s t e r ) ( ) ( h i g h s d a e a c k n o w l e d g n o t a l o w s d a e a c k n o w l e d g a ? ? s t o p s t o p m a p : m e m o r y a d d r e s s p o i n t e r ( t h e t a r g e t r e g i s t e r a d d r e s s i n s l a v e d e v i c e ) s c l 1 a d a t a s l a v e a d d r e s s s t a r t s t o p 0 a a m a p s d a 3 . a u t o r e a d t r a n s a c t i o n ( = w r i t e - m a p - o n l y + n b y t e r e a d t r a n s a c t i o n ) s l a v e a d d r e s s s t o p s t a r t d a t a d a t a d a t a d a t a d a t a a
cm65 35 usb audi o chip page 35 / 57 www.cmedia.com.tw copyright? c - media electronics inc. 6.9.2 i2c - master read with clk_sync m ode 6.9.3 i 2 c master device address and control register address: 0x80 bits r/w bit mnemonic description default 7 - 1 r/w sa_reg the target slave device address. 0xa8 (por) 0 r/w sa_reg 1: read, 0: write 1b0 6.9.4 i 2 c master memory address pointer (map) register address: 0x81 bits r/w bit mnemonic description default 7 - 0 r/w map_reg the register low byte address of salve device to be read or written. 8b0 6.9.5 i 2 c master memory address pointer (map2) register address: 0x82 bits r/w bit mnemonic description default 7 - 0 r/w map2_reg the register high byte address of salve device to be read or written. 8b0 6.9.6 i 2 c master data register address: 0x83 ~ 0x92 bits r/w bit mnemonic description default 7 - 0 r/w data0~ data15 the data read from or written to the slave device. 8b0
cm65 35 usb audi o chip page 36 / 57 www.cmedia.com.tw copyright? c - media electronics inc. 6.9.7 i 2 c master control and status register 0 address: 0x93 bits r/w bit mnemonic description default 7 - 0 r/w i2c_ctrl_reg1 data length of read/write command 8h1: 1 byte, minimum length 8h2: 2 bytes 8hfe: 254 bytes 8hff: 256 bytes, maximum length 6.9.8 i 2 c master control and status register 1 address: 0x94 bits r/w bit mnemonic description default 7 r/w i2c_start trigger i 2 c read/write command 0 - >1: trigger i 2 c read/write command. 1 - >0: i 2 c interface had completed current task. 0 : i 2 c interface is idle and ready for work. 1 : i 2 c interface is running. 1b0 2 c interface 0 : not reset i 2 c interface 1 : reset i 2 c interface 1b0 : 8 - bit map 1 : 16 - bit map 1b0 1b1 2 c speed mode 0 : standard mode, 100khz 1 : fast mode, 400khz 1b0 2 r/w map_only map only write command 0 : write command. 1 : map only write command. 1b0 : read command. 1 : auto read command. 1b1 : no error 2 : slave nack error occur 1b0 6.9.9 i 2 c master download control and status register address: 0x95 bits r/w bit mnemonic description default 7 r/w i2c_mas_sel i2c master/slave select 1b1 st 8 bytes data or 2 nd 1b0
cm65 35 usb audi o chip page 37 / 57 www.cmedia.com.tw copyright? c - media electronics inc. 8 bytes data. if the flag index its transmitting the 2 nd 8 bytes data, then f/w can prepare the next 8 bytes data into 1 st 8byte buffer. flag_ready (wo): flag to index f/w has prepared next data ready. after prepare done, f/w need set this bit to index the data had been written. if f/w didnt catch on when all data has been transmitted, the i 2 c clock would be keep low to till it ready. 5:4 r/w ld_block download to which block of sram. 00: load to 1 st 8kb block. 01: load to 2 nd 8kb block. 10: load to 3 rd 8kb block. 11: load to 4 th 8kb block. 2b00 (por) 3 ro chksum_err check sum error 1. if in ld_phase, the check sum value was calculated by i 2 c load data. 2. if in chk_phase, the check sum value was calculated by sram read content. 1b0 2 ro chk_finish check phase done 1: finish download data check 1b0 1 r/w chk_phase mcu select check phase to read sram data for check - sum check. 1: enable (after disable ld_phase) 0: set 0 after complete 1b0 (por) 0 r/w ld_phase mcu select load phase to access sram from download. 1: enable 0: set 0 after complete 1b0 (por) 6.9.10 i 2 c master clock period setting register address: 0x96 bits r/w bit mnemonic description default 7 w chg_enable mcu can program i 2 c clock; 1b1: 1b0 1b0 : spi download 1b1 : i 2 c download 1b0 2 c - master clock period. the clock period=83.3*5*(chg_freq+1) ex: chg_freq = 6d48 hw limitation chg_freq >= 6h3 6h0
cm65 35 usb audi o chip page 38 / 57 www.cmedia.com.tw copyright? c - media electronics inc. 6.9.11 i 2 c slave mode 7 - bit slave address = 7b0001000 to 7b0001011 CM6535 can serves as a slave device with bit rate up to 400kbps (fast mode). external mcu can write data to CM6535 or read data from CM6535 (no size limitation in i 2 c interface). since host side and mcu can both access to all the internal registers. CM6535 will transfer an interrupt to internal mcu until the int bit of i 2 c control r egiste r ha s been clean ed by internal mcu. the interrupt will be trigger when write transaction is done or detect read - slave - address. the main usage of 2 - wire slave bus is to become the interface between the CM6535 and a n external micro control unit (emcu). 6.9.12 i 2 c slave d ata register address: 30~33h bits r/w bit mnemonic description default 31:0 r/w mcu_data0~f the data received from or transmitted to master device. this register cannot be written when 2 - wire slave serial bus status is busy. 0000h (por) 6.9.13 i 2 c slave s tatus register address: 34~35h bits r/w bit mnemonic description default 15 reserved 1b 14:12 r reserved 0h 11 r/w thld_int_mask threshold interrupt mask: 1: mask ; 0: non - mask ; default :0 0b (por) 10 r write_data_ready interrupt happened, auto - cleared after read 0b (por) 9 r/w i2c_s_reset 0: 2 - wire serial bus in normal operation (default) 1: 2 - wire serial bus in reset state 0b (por) 8 r/w dri_tran_st i nitiated transaction status 1: the last initiated transaction failed, write 1 to clear. 0b (por) 7 r/w rd_tran_st read transaction status 1: a new read transaction received, write 1 to clear. 0b (por) 6 r/w wr_tran_st write transaction status 1: a new write transaction received, write 1 to clear. 0b (por) 5:1 r data_len the data length of the last write transaction received, 00000: 1 byte (map only) 00001: 2 byte (map + 1 byte data) 00010: 3 byte (map + 2 byte data) 00011: 4 byte (map + 3 byte data) 00100: 5 byte (map + 4 byte data) ?
cm65 35 usb audi o chip page 39 / 57 www.cmedia.com.tw copyright? c - media electronics inc. **note: when i 2 c issue interrupt to mcu, mcu need s to read the data numbers that threshold data count specified. and wait s another interrupt until the total data transfer completed. 6.9.14 i 2 c slave memory address pointer (map) register address: 36h bits r/w bit mnemonic description default 7:0 r/w mcu_map the memory addresses of the read or write transactions from mcu. address 0 is reserved for initiated transaction. 00h (por) 6.9.15 i 2 c slave s tatus register address: 37h bits r/w bit mnemonic description default 7 r/w sync_en synchronization enable 1: enable (the synchronization selection bit will decide the method adopted). 0: disable (mcu and arc should guarantee no data lost themselves). 1b (por) 6 r/w int_polarity the polarity control of pin int_out (initiated transaction interrupt), 0: high active, 1: low active 0b (por) 5:4 r/w slave_addr slave device address 00: select 0001000 (10h) as slave address 01: select 0001001 (12h) as slave address 10: select 0001010 (14h) as slave address 11: select 0001011 (16h) as slave address 01b (por) 3 r/w sync_sel synchronization method selection 1: data synchronization. when this bit is one, if the current transaction has not been serviced by arc, the clock line of the 2 - wire serial bus will be pulled low. under this situation, the mcu cannot start a new transaction or continue the current read transaction until the clock line goes bac k to high. 0: ready pin synchronization. if the mcu cannot support open drain 2 - wire serial bus, this bit should be set to zero. in this instance , the mcu cannot start a new transaction or continue the current read transaction until the pin xslave_rdy goe s high to signal that the driver has serviced the current transaction. driver should use driver acknowledge to signal the processing interrupt mask 0: interrupt will happen at a read/write transaction received or a driver initiated transaction failed 1: interrupt will not happen 0b (por) 1 r/w dri_init_tran driver initiated transaction write 1 to start driver initiated transaction. this bit is cleared automatically, after arc initiated transaction starts. the arc initiated transaction should be issued only when the 2 - wire slave serial bus is idle. otherwise, it will be ignored. the arc i nitiated transaction will cause pin int_out to send out an interrupt for mcu. after mcu responded with a write - map - address - 0 - only transaction and a subsequent read transaction, interrupt 0b (por)
cm65 35 usb audi o chip page 40 / 57 www.cmedia.com.tw copyright? c - media electronics inc. int_out will be de - asserted. however, if the mcu does not act as what is expected (a write map - address - 0 - only transaction and a subsequent read transaction), the interrupt int_out will be still de - asserted, but the arc initiated transaction status is used to signal a fail status to arc. in this case, the driver should consi der to repeat the failed driver initiated transaction again. 0 r/w ack driver acknowledge means driver has processed the current transaction. write 1 to acknowledge. this bit will be cleared automatically. 0b (por) i2c example for master mode: write 2 bytes: (slave address = 92, map address = 01, data = 55, aa) write 0x80 = 92 (slave address) write 0x81 = 01 (map address) write 0x83~0x84 = 55 aa (data register) write 0x93 = 02 (data length 2 bytes) write 0x94 = 92 (i2c start) read 2 bytes: (sla ve address = 92, map address = 01) write 0x80 = 93 (slave address) write 0x81 = 01 (map address) write 0x93 = 02 (data length 2 bytes) write 0x94 = 92 (i2c start) read 0x83~0x84 (data register)
cm65 35 usb audi o chip page 41 / 57 www.cmedia.com.tw copyright? c - media electronics inc. 6.10 spi i nterface the spi interface is used to transfer control data between the cm653 5 and external codec. in a spi interface there is only one central clock source producin g a reference clock to which spi data processing is synchronized. this clock is often referred to as the mcu clock, e.g. for spi cl ock 12 mhz, w hen the mcu c loc k is equal to 48mhz an d spi clock div4. 6.10.1 spi registers descriptions address: 3 8~3b h bits r/w bit mnemonic description default 31 - 0 r/w data0 ~data3 the data (which include address, r/w, and data bits) written to or read from the codec. the bits in this register should be interpreted according to the individual codec. the content of this register, after a write operation completes, has no meaning. the content of this registe r, after a read operation completes, should reference the document of individual codec to see how many bits in this register is valid . 0x0000 0 000 (por) 6.10.2 spi c ontrol r egister 0 address: 3ch bits r/w bit mnemonic description default 7 r/w slv_mst spi master/slave mode 0: master mode 1: slave mode 1b1 1b1 1b0 1b0 1b0 th bit 1: rs/a0==1 for 8 th bit 1b0 0: mcu cant read spi data 1b0 0: mcu cant write spi data 1b0
cm65 35 usb audi o chip page 42 / 57 www.cmedia.com.tw copyright? c - media electronics inc. 6.10.3 spi c ontrol r egister 1 address: 3dh bits r/w bit mnemonic description default 7 r/w spi_start trigger spi read/write command 0 - >1: trigger spi read/write command 1 - >0: spi interface had completed current task 0 : spi interface is idle and ready for work 1 : spi interface is running 1b0 1b1 1b0 2b00: by mcu clk div 4 2b01: by mcu clk div 12 2b10: by mcu clk div 16 2b11: by mcu clk div 20 2b0 1b0 1b0 1b0 6.10.4 spi i nterrupt address: 3eh bits r/w bit mnemonic description default 7 r/w cpol clock polarity 1b1 1b1 2b10 1b0 1b0 1b1 1b1
cm65 35 usb audi o chip page 43 / 57 www.cmedia.com.tw copyright? c - media electronics inc. 2. bit[0]: when spi interface is in master mode, spi interrupt will happened when bit[0] ==1 and every spi master command completed. interrupt (hid) would be cleaned once address 0x10 was written. 6.10.5 spi c ontrol r egister 3 address: 3fh bits r/w bit mnemonic description default 7 - 0 r/w data_len the data length of read/write, 0000_0000: reserved 0000_0001: 1 bytes 0000_0010: 2 bytes 0000_0011: 3 bytes . . . 1111_1111:255 bytes 8d0 spi example for master mode: write 3 bytes: (address = 92, data = 55,aa) write 0x38~0x3a = 92 55 aa (data register) write 0x3f = 03 (write 3 bytes length) write 0x3d = a0 (spi start) read 3 bytes: (address = 92) write 0x38= 92 (data register) write 0x3f = 03 (read 3 bytes length) write 0x3d = 80 (spi start) read 0x38~0x3a
cm65 35 usb audi o chip page 44 / 57 www.cmedia.com.tw copyright? c - media electronics inc. 6.11 gpio 6.11.1 gpo d ata r egister address offset: c0 - c1h bits r/w bit mnemonic description default 15:0 r/w gpo_0_reg gpo_1_reg gpo data register which represents 16h0 6.11.2 gpi data register address offset: c2 - c3h bits r/w bit mnemonic description default 15:0 r gpi data register which represents 16h0 6.11.3 gpio d irection c ontrol r egister address offset: c4 - c5h bits r/w bit mnemonic description default 15:0 r/w gpoe_0 gpoe_1 gpio output enable register which represents for pin xgpio[15:0] 1: the corresponding pins are used as output s 0: the corresponding pins are used as input s 16h0 6.11.4 gpio i nterrupt e nable m ask r egister address offset: c6 - c7h bits r/w bit mnemonic description default 15:0 r/w gpi_en gpio_e, gpio interrupt enable mask which represents for pins, xgpio[15:0] 1: enable, 0: disable 16h0 6.11.5 gpio d ebouncing r egister address offset: c8 - c9h default value: 0000h (msb - > lsb) bits r/w bit mnemonic description default 15:0 r/w gpi_deb enable the clock scale of mi ll isecond (32 ms) for debouncing, default 1 1: enable, 0: disable 16h0 6.11.6 gpi r emote c hoose address offset: 0xe2~e3h bits r/w bit mnemonic description default 15:0 r/w gpi_rwl gpi_rwh d0==1b1:gpi[0] remote wake up d1==1b1:gpi[1] remote wake up d2==1b1:gpi[2] remote wake up 16h0
cm65 35 usb audi o chip page 45 / 57 www.cmedia.com.tw copyright? c - media electronics inc. enable d d3==1b1:gpi[3] remote wake up enable d d4==1b1:gpi[4] remote wake up enable d d5==1b1:gpi[5] remote wake up enable d d6==1b1:gpi[6] remote wake up enable d d7==1b1:gpi[7] remote wake up enable d d8==1b1:gpi[8] remote wake up enable d d9==1b1:gpi[9] remote wake up enable d d10==1b1:gpi[10] remote wake up enab le d d11==1b1:gpi[11] remote wake up enable d d12==1b1:gpi[12] remote wake up enable d d13==1b1:gpi[13] remote wake up enable d d14==1b1:gpi[14] remote wake up enable d d15==1b1:gpi[15] remote wake up enable d 6.11.7 gpio p ull - up/ d own address offset: 0xe4 bits r/w bit mnemonic description d efault 7 r/w gpio_pd0[7] gpio_7 pad control 1b1 : floating ; 1b0 : 75k pull up 1b1(por) 1b1 : floating ; 1b0 : 75k pull up 1b1(por) 1b1 : floating ; 1b0 : 75k pull up 1b1(por) 1b1 : floating ; 1b0 : 75k pull up 1b1(por) 1b1 : floating ; 1b0 : 75k pull up 1b1(por) 1b1 : floating ; 1b0 : 75k pull up 1b1(por) 1b1 : floating ; 1b0 : 75k pull up 1b1(por) 1b1 : floating ; 1b0 : 75k pull up 1b1(por) bits r/w bit mnemonic description d efault 7 r/w gpio_pd1[7] gpio_15 pad control 1b1 : floating ; 1b0 : 75k pull up 1b1 1b1 : floating ; 1b0 : 75k pull up 1b1(por) 1b1 : floating ; 1b0 : 75k pull up 1b1(por)
cm65 35 usb audi o chip page 46 / 57 www.cmedia.com.tw copyright? c - media electronics inc. 4 r/w gpio_pd1[4] gpio_12 pad control 1b1 : floating ; 1b0 : 75k pull up 1b1(por) 3 r/w gpio_pd1[3] gpio_11 pad control 1b1 : floating ; 1b0 : 75k pull up 1b1(por) 2 r/w gpio_pd1[2] gpio_10 pad control 1b1 : floating ; 1b0 : 75k pull up 1b1(por) 1 r/w gpio_pd1[1] gpio_9 pad control 1b1 : floating ; 1b0 : 75k pull up 1b1(por) 0 r/w gpio_pd1[0] gpio_8 pad control 1b1 : floating ; 1b0 : 75k pull up 1b1(por) address offset: 0xe6 bits r/w bit mnemonic description d efault 7 r/w gpio_pd2[7] gpio23 pad control 1b1 : floating ; 1b0 : 75k pull up 1b1 1b1 : floating ; 1b0 : 75k pull up 1b1(por) 1b1 : floating ; 1b0 : 75k pull up 1b1(por) 1b1 : floating ; 1b0 : 75k pull up 1b1(por) 1b1 : floating ; 1b0 : 75k pull up 1b1(por) 1b1 : floating ; 1b0 : 75k pull up 1b1(por) 1b1 : floating ; 1b0 : 75k pull up 1b1(por) 1b1 : floating ; 1b0 : 75k pull up 1b1(por)
cm65 35 usb audi o chip page 47 / 57 www.cmedia.com.tw copyright? c - media electronics inc. 6.12 arbitrary s ine - tone g enerator there are four (4) memory banks to store user defined waveform in cm653 5 design. this function would generate waveform data that is desired to be hear d from earphones. for example , when function keys were pressed or do other operations , u ser can predefine two different waveforms with 96k and 88.2k sampling rates and stores it in corresponding memory banks. the waveform data format must comply with the following specifications : 1. 16 bits pcm with 2s complement 2. first word must define wavefor m length (length[9:0]= {byte1[2:0], byte0[7:0]}) 3. waveform length must less than 2046 4. four memory banks bank1: 0x6000~0x67ff (length: 0x6000~0x6001, waveform data 0x6002~0x67ff) bank2: 0x6800~0x6fff (length: 0x6800~0x6801, waveform data 0x6802~0x6fff) bank3 : 0x7000~0x77ff (length: 0x7000~0x7001, waveform data 0x7002~0x77ff) bank4: 0x7800~0x7fff (length: 0x7800~0x7801, waveform data 0x7802~0x7fff) g enerating sine - tone is based on a look - up table and the step size of look - up table for different sampling rates is adjusted automatically.
cm65 35 usb audi o chip page 48 / 57 www.cmedia.com.tw copyright? c - media electronics inc. 6.13 tri - c olor ed led c ontrol s etting pwm function is generated by led counter and output the pwm signal to gpio pin. the 8 - bit counter counts modulus 256 controlled by led freq, led duty register. the led unit register control s pwm resolution. when the led freq register value is equal to the led duty register (high), the pwm output also goes high. when the led freq, led duty register reaches zero, the pwm output is forced to go low. the low - to - high ratio (duty) of the pw m output is led duty/led freq. led duty led freq led unit (256 step) pwm duty range 00h ffh 00:10.5ms 01:5.45ms 10:2.73ms 11:1.36ms 00h/ffh ~feh/ffh 01h ffh 80h ffh feh ffh the output d uty of pwm has different timing s . duty range is from 0/256~255/256. l e d d u t y / l e d f r e q = 0 0 h / f f h l e d d u t y / l e d f r e q = 0 1 h / f f h l e d d u t y / l e d f r e q = 8 0 h / f f h l e d d u t y / l e d f r e q = f e h / f f h
cm65 35 usb audi o chip page 49 / 57 www.cmedia.com.tw copyright? c - media electronics inc. 6.14 r eset 6.14.1 w atchdog reset timer the watchdog timer is a 15 - bit counter that is incremented every 24 or 384 clock cycles. it is used to provide the system supervision in case of software or hardware upset. if the software wa s not able to refresh the w atchdog t imer after 786336 or 12581376 clock cycles (65ms or 1s when using 12mhz clock), an internal reset is generated. p o w e r v s s v d d w a t c h d o g o v e r f l o w t i m e w d t r e s e t n o r m a l r u n f l a s h i n i t i a l t i m e ( r e a d 1 6 k f i r m w a r e f r o m i n t e r n a l f l a s h ) r e s e t r e a d y f l a s h i n i t i a l t i m e ( r e a d 3 2 k f i r m w a r e f r o m i n t e r n a l f l a s h ) r e s e t r e a d y 5 5 m s e c 9 5 m s e c d e f a u l t 1 s e c
cm65 35 usb audi o chip page 50 / 57 www.cmedia.com.tw copyright? c - media electronics inc. 7 electrical c haracteristics 7.1 absolute maximum ratings test conditions: dv50 = 5v, av50 = 5v, dgnd =0v, ta=+25oc parameter symbol min. typ max. unit storge temperature t s - 25 - 150 o c operating ambient temperature t a - 15 25 70 o c digital supply voltage(dv50) 4.5 5.0 5.5 v analog supply voltage(av50) 4.5 5.0 5.5 v i/o pin voltage - gnd - 3.3 v esd (body mode) 4000 v esd (machine mode) 200 v 7.2 recommended operation conditions parameter symbol min. typ max. unit digital supply voltage(dv50) - 5 v analog supply voltage(av50) 5 v operating ambient temperature 25 o c crystal clock - 12.000 mhz 7.3 power consumption test conditions: dv50=5v, av50 = 5 v, dgnd =0v, ta=+25 o c , mcu clock = 12mhz. sample rate=48khz, 16bits, operation: hp - out playback+mic - in recording, eq disable, spdif out disable , no loading parameter min. typ max. unit total power consumption (including p layback and r ecording) - 65.9 = digital 27.9ma + analog 38ma - ma standby power consumption (excluding p layback and r ecording) - 64 - ma suspend mode power consumption - 2.4 - ma 7.4 dc characteristics test conditions: dv50=5v, v dd = 3.3 v, dgnd =0v, ta=+25 o c , v dd = 3.3v **note: dvdd18,avdd36,av42_da,av36_dal,av36_dar without current drivecapacity parameter symbol min. typ max. unit operation voltage range dvdd 4.5 5 5.5 dc input voltage range (gpio,i2c,spi,spdif) dcvin - 0.3 5.5 v input high - level voltage (gpio,i2c,spi,spdif) vih 2 2 v input low - level voltage (gpio,i2c,spi,spdif) vil 0.8 0.8 v output high - level voltage (gpio,i2c,spi,spdif) voh 2.4 - 3.6 v output low - level voltage (gpio,i2c,spi,spdif) vol 0 - 0.4 v output source current (gpio, i2c,spi,spdif) ioh 8 ma output sink current (gpio, i2c,spi,spdif) iol 8 ma vreg33 driver current ivreg 10 ma
cm65 35 usb audi o chip page 51 / 57 www.cmedia.com.tw copyright? c - media electronics inc. 7.5 analog audio parameter symbol pin name limit values unit test conditions min. typ. max signal reference voltage xvag xvag 1.65 1.75 1.85 v rload>> 10 m ? microphone input clipping level (at minimum input volume, i.e., 0 db) vmi xmicl xmicr 2.828 vpp volume = 0 db line input clipping level (at minimum input volume, i.e., 0 db) vmi xlinl xlinr 2.828 vpp volume = 0 db analog output voltage ac vao xlnoutl xlnoutr 2.828 vpp microphone input impedance mii xmicl xmicr 20 45 k ? microphone a - a input impedance maii xmicl xmicr 20 k ? headphone output impedance hpoi xlnoutl xlnoutr 32 ? volume = db 7.6 usb transceiver parameter symbol pin name limit values unit test conditions min. typ. max regulator voltage xv33 xv33 3.0 3.3 3.6 v cl =10uf driver output impedance including the 22 ? external serial resistor ro d+/d ? 24 40 ? static, low or high rise and fall times tr/tf 3 10 19 ns cl = 50 pf, driver mode rise/fall time matching ma_trt f 90 110 % cl = 50 pf, driver mode crossover voltage vxover 1.30 1.75 2.0 v cl = 50 pf, driver mode differential receiver common - mode range vcm_dr ec 0.8 2.5 v single - ended receiver threshold voltage vt_srec 0.8 2.0 v switchable pull - up resistor rpu vreg, d+ 1.5 k ?
cm65 35 usb audi o chip page 52 / 57 www.cmedia.com.tw copyright? c - media electronics inc. 7.7 microphone bias parameter symbol pin name limit values unit test conditions min. typ. max open circuit voltage microphone bias vmicbias micbias 2.55 2.75 2.95 v output current microphone bias imicbias micbias 1.25 ma rmin=2.2k ? output impedance microphone bias routmicb micbias 600 650 700 ? power supply rejection ratio for microphone bias psrrmicb avdd, micbias 100 db internal regulators active, at maximum load current (0.5 ma), 1 khz sine wave at 100 mvrms
cm65 35 usb audi o chip page 53 / 57 www.cmedia.com.tw copyright? c - media electronics inc. 8 audio performance 8.1 dac audio quality ta=25 , dv50=5v, av50=5v, equalizer disable , typical fs/bit - depth=48khz/16bit (except remarked in test conditions), master volume= 0db, platform dell desktop 32bws02, 4g ram, windows 8.1 cht items test conditions test values unit min. typ. max. full s cale output voltage 10k ? loadin 1.04 vrms 32 ? loading 0.99 vrms thd+n @ - 3db full scale 10k ? loading ? loading ? loading ? loading ? loading ? loading ? loading ? loading ? loading ? loading ? loading ? loading ? loading
cm65 35 usb audi o chip page 54 / 57 www.cmedia.com.tw copyright? c - media electronics inc. 8.2 adc audio quality ta=25 , dv50=5v, av50=5v, input test signal is 997hz sine wave, measure bandwidth is 120hz to 20khz, equalizer disable, agc off , mic gain= 0db, typical fs/bit - depth=48khz/16bit (except remarked in test conditions) platform dell desktop 32bws02, 4g ram, windows 8.1 cht items test conditions test values unit min. typ. max. full s cale input voltage microphone 0.74 vrms full scale input voltage line input 0.7 vrms thd+n @ - 3db full scale microphone [120hz ~ 20khz] - 83 (@1khz) db thd+n @ - 3db full scale line input[20hz ~ 20khz] - 8 4 (@1khz) db dynamic range ( with - 60dbfs input signal ) microphone [997hz] a - weighted 88 db dynamic range ( with - 60dbfs input signal ) line input[997hz] a - weighted 89 db sampling frequency accuracy microphone [997hz] - 0.0032 - 0.00 69 % line input[997hz] - 0.0038 +0.0076 % channel separation (crosstalk) microphone , 20~20khz - 80 db line input , 20~20khz - 84 db frequency response microphone , 20~20khz 0.035 (20hz) - 0.527 (20khz) db line input, 20~48khz 0.414 (20hz) - 0.581 (20khz) db passband ripple range microphone 0.264 db passband ripple range line input 0.265 db
cm65 35 usb audi o chip page 55 / 57 www.cmedia.com.tw copyright? c - media electronics inc. 8.3 a - a path audio quality ta=25 , dv50=5v, av50=5v , microphone - in to line - o ut , 10kohms loading, master volume=0db, mic gain=0db , typical fs/bit - depth=48khz/16bit platform dell desktop 32bws02, 4g ram, windows 8.1 cht items test conditions test values unit min. typ. max. full scale output voltage microphone to line out 1.05 vrms full scale output voltage line input to line out 1.01 vrms thd+n @ - 3db full scale microphone to line out 20~20khz - 89 db thd+n @ - 3db full scale line input to line out 20~20khz - 89 db dynamic range ( with - 60dbfs input signal ) microphone to line out a - weighted 93 db dynamic range ( with - 60dbfs input signal ) line input to line out a - weighted 93 db channel separation(crosstalk) microphone to line out 20~20khz - 90 db channel separation(crosstalk) line input to line out 20~20khz - 90 db frequency response microphone to line out 20~20khz - 0.036 - 0.133 db frequency response line input to line out 20~20khz +0.007 - 0.104 db passband ripple microphone 20~20khz 0.002 db passband ripple line input 20~20khz 0.001 db
cm65 35 usb audi o chip page 56 / 57 www.cmedia.com.tw copyright? c - media electronics inc. 9 packag e dimension model number package operating ambient temperature supply range CM6535 64 - pin lqfp 7mm7mm1.4mm (plastic) - 15 c to +70 c dvdd = 5v, avdd = 5v outline dimensions * dimensions shown in inches and ( mm ) 64 - lead thin plastic quad flatpack (lqfp) package dimension o f CM6535
cm65 35 usb audi o chip page 57 / 57 www.cmedia.com.tw copyright? c - media electronics inc. end of datasheet c - media electronics inc. 6f., 100, sec. 4, civil boulevard, taipei, taiwan 106 r.o.c. tel +886 - 2 - 8773 - 1100 fax +886 - 2 - 8773 - 2211 e - mail sales@cmedia.com.tw disclaimer: information furnished by c - media electronics inc. is believed to be accurate and reliable. however, no responsibility is assumed by c - media electronics inc. for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of c - media. trademark and registered trademark are the property of their respective owners.

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